This application claims priority from European patent application number 00106884.0, filed Mar. 31, 2000, which is hereby incorporated herein by reference in its entirety.
The present invention relates to hardware development and chip design. In particular, it relates to improvements concerning the logic and timing verification as testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment.
Any hardware design which is subjected to modern design technology has to fulfill a plurality of requirements in order to be up to date and attractive for the client. Thus, any hardware should have a good performance in relation to its prize, it should be robust and reliable, in particular when high-end server logic chips are concerned. In order to create a reliable hardware it must be testable as well as a general requirement for any hardware.
In view of the general must to produce faster logic chips any possibilities are exploited in order to contribute to this aim.
One contribution amongst others is to implement dynamic logic circuits into a logic chip because this is a hardware which performs faster than standard static logic circuits.
A static logic circuit is operated in a way in which every node of it is always connected to either ground or the supply voltage Vdd. Dynamic logic circuits, however, have nodes which are not grounded or connected to Vdd permanently, but instead, the dynamic nodes are precharged to either ground or Vdd and then, during operation of the dynamic logic circuit a node is either drawn to potential ground or Vdd or stays on the precharge level, depending on the desired switching mechanism. During evaluation time, a node staying at the precharge level is said to be floating since precharge is not active and the evaluation tree is noncontacting.
This property of dynamic logic circuits, however, makes testing of the hardware difficult. In particular, when a hardware is subjected to timing analysis by traditional testing utilities and machinery, a prerequisite is that the nodes which are scanned and thus tested for reliability are non-floating. Thus, in prior art, it is not possible to build dynamic logic in risky locations, for example where combinatorial logic is used. In combinatorial logic circuits every node between any predefined number of gates has to be tested in order to make sure that the circuit or parts of it deliver the expected results. Thus, in such risky locations standard static CMOS logic is used.
The growing performance requirements, however make the use of dynamic circuits in more and more selected places desirable. Array structures are an ideal place where dynamic circuits can be used advantageously. The timing can be very structured, the path length is very well known and physical dimensions are fixed and always the same at comparable locations because an array comprises a large number of repetitions of its inner core structure.
Thus it is desirable to embed dynamic logic circuits into static circuits while concurrently keeping the testability provided by LSSD compliant hardware.
It is thus an object of the present invention to enable dynamic hardware to be embedded into static hardware which is compliant to the LSSD concept.
An object of the invention is achieved by the features stated in enclosed independent claims. Further advantageous arrangements and embodiments of the invention are set forth in the respective subclaims.
According to one aspect of the present invention a technical solution for embedding dynamic logic circuits into a static environment is provided in which the dynamic logic appears encapsulated within clocked macros a term which is used in here as comprising dynamic macros amongst others. The clocked macros are bounded at both input and output by latches, keeping all input and output signals to the clocked macro static. This inventional concept allows to sprinkle dynamic logic at a plurality of locations into each a static hardware environment. In other words, islands of dynamic logic appear in a sea of static logic.
Thus, the analysis methods for timing and logic simulation during chip design can be the same as used for static logic, and in particular the advantageous LSSD testing methods can be used.
Any LSSD circuit configuration requires that all logic paths the input- and output-nodes of which are required to be testable according to the LSSD methods are bounded by a pair of latches, each latch being responsive to an xe2x80x98independentxe2x80x99 clock. In the example shown and described in here, these pairs are exemplarily chosen to be master-slave latches. Master/master pairs would, however, work as well. The present invention is based on the idea to provide a frame around the dynamic logic circuit which provides for properly feeding the dynamic logic circuit with one or more input signals in line with the static logic slave clock and to feed the output signal of the dynamic logic circuit to the posed connected static circuit such that the dynamic circuit output signal is able to be latched into a master latch.
In particular, this is achieved by processing static input signals with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, feeding the wave-formatted signal to the dynamic logic circuit, and converting the dynamic logic evaluation output signal back to a static signal. The conversion should advantageously be performed such that the dynamic logic evaluation output can be latched by the clock signal of the static embedding circuit, i.e. by the next master latch.
Thus, some input adapter means and some output adapter means are associated with the dynamic logic circuit and are connected with its input and output, respectively.
Advantageously the input adapter means can be a clock chopper and a wave formatter, whereas the output adapter means is a set/reset-latch.
In order to provide for a LSSD compliant chip design the slave clock signal is applied to the dynamic logic circuit at predetermined points in time. The slave clock signal passes through the dynamic logic circuit, combined with the input signals and generates its output signal which is converted back to a static signal (extract clock) by a Set/Reset latch allowing to feed it into the master latch. The time regime for the clocked macro is determined by the leading edge of the slave clock signal.
Such an embedding makes the dynamic logic circuit, i.e. the clocked macro appearing as a static circuit which can be combined with other static circuits andxe2x80x94can be tested according to LSSD methods.
The implementation as disclosed in the present invention supports full LSSD testing, including random selftest, at any cycle time equal or longer than the functional cycle.
The clocked macro can be isolated from the surrounding logic, during test to allow individual test sequences for the clocked macro and the macro surrounding logic. The latches feeding the clocked macro as the S/R macro output latches get an additional slave latch to allow independent scanning. The master as the slave scan-clock and the macro clock are independent from C1, C2 clocks during test. To test the macro only, the respective stimuli pattern are scanned into the latches driving the macro. After firing the macro clock the result is received in the output latch and can be observed after scanning the data out. The macro gets into a defined state after power on, since default of all restore devices is ON, precharging all dynamic nodes. No additional test signals as for example, reset after POWER-ON, are necessary. Single clock cycles, as the typical test sequence scan-in, execute one cycle, and scan out are possible.